[Librecores Discussion] RISC-V Port to Parallela GSoC'16 Project

Elias Kouskoumvekakis eliaskousk at gmail.com
Wed Jun 1 21:59:35 CEST 2016

Hello everyone,

Google's Summer of Code 2016 has started last week and I just wanted to
announce here my FOSSi project "RISC-V port to Parallela" which as the name
suggests will have me working for the next 3 months with the goal of
successfully porting and integrating a RISC-V ISA based core from UC
Berkeley inside the Zynq FPGA device of the Parallela board.

You can find out more about the project and see my progress each week on my
blog which I launched last week. I would appreciate any comments and / or
suggesting you might have. Even reading some of my weekly posts is enough
to motivate me working hard during the hot summer days in Athens!


Best regards,
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