[Librecores Discussion] Starting point for a simple ASIC SoC

Olof Kindgren olof.kindgren at gmail.com
Thu Jun 16 22:40:40 CEST 2016


Hi,

We're thinking of doing a mixed-signal ASIC with a simple CPU to
control some aspects of the analog parts. The digital parts will
consist of a CPU, memory + some GPIO, memory and probably some
mechanism for loading and debugging programs (e.g. boot ROM, SPI
controller, jtag+debug interface)

What I wonder now is how much I can reuse from existing ASIC
implementations. First example that comes to mind is Pulp/Pulpino, but
there seem to have been plenty of other tapeouts, especially from
academia, of OpenRISC and RISC-V systems. As I don't have very much
experience of the ASIC backend flow, I'm not sure to which extent
things can be reused at all. Can I reuse existing netlists, floor
plans or even parts of the mask sets?


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