[Librecores Discussion] Starting point for a simple ASIC SoC

Davide Rossi davide.rossi at unibo.it
Fri Jun 17 08:00:03 CEST 2016


Hi Olof,

In terms of digital implementation flow we can provide you the synthesis
scripts that are
required to generate the netlist in the specific technology node you
will be using for your
tape-out and backend scripts for encounter. Off couse we can also give
you some support
for floorplanning and other things, but usually floorplanning is
extremaly chip dependent
eapecially in mixed signal chips where the main constraint comes from
the analog part.

BTW, just for curiosity, what is the application you are planning for
this chip?

Cheers,
Davide

Il 16/06/2016 22:40, Olof Kindgren ha scritto:
> Hi,
>
> We're thinking of doing a mixed-signal ASIC with a simple CPU to
> control some aspects of the analog parts. The digital parts will
> consist of a CPU, memory + some GPIO, memory and probably some
> mechanism for loading and debugging programs (e.g. boot ROM, SPI
> controller, jtag+debug interface)
>
> What I wonder now is how much I can reuse from existing ASIC
> implementations. First example that comes to mind is Pulp/Pulpino, but
> there seem to have been plenty of other tapeouts, especially from
> academia, of OpenRISC and RISC-V systems. As I don't have very much
> experience of the ASIC backend flow, I'm not sure to which extent
> things can be reused at all. Can I reuse existing netlists, floor
> plans or even parts of the mask sets?
> _______________________________________________
> Discussion mailing list
> Discussion at lists.librecores.org
> https://lists.librecores.org/listinfo/discussion



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