[Librecores Discussion] Starting point for a simple ASIC SoC

Davide Rossi davide.rossi at unibo.it
Fri Jun 17 11:08:19 CEST 2016


Hi Olof,

We have already implemented PULPino in several technology nodes (130,
65, 28), the
system verilog description of pulpino is completely technology
independent, only few
clock gating cells needed for power management have to be inserted
manually in a
couple of files. So, PULPino can be implemented in any technology node
assuming
that it has a library of standard cells and SRAMs with frontend and
backend views.
I see no major blocking problems and as i said we can support you for
synthesis and P&R.

Cheers,
Davide

Il 17/06/2016 09:26, Olof Kindgren ha scritto:
> Hi Davide,
>
> Thanks for the explanations and your offer to help out.
>
> I realized now that I forgot to mention one important aspect of the
> project. It's a research project with ties to commercial companies, so
> I'm not sure how much I can share about the project itself, but I'll
> let you know when I know what I can share. Also, I'm not sure I even
> understand the analog parts to be honest. :) The relevant info I have
> is that we will be using 130nm BiCMOS. Would the usage or the process
> be a problem if I would want to base it on Pulp(ino)?
>
> //Olof
>
>
>
> On Fri, Jun 17, 2016 at 8:00 AM, Davide Rossi <davide.rossi at unibo.it> wrote:
>> Hi Olof,
>>
>> In terms of digital implementation flow we can provide you the synthesis
>> scripts that are
>> required to generate the netlist in the specific technology node you
>> will be using for your
>> tape-out and backend scripts for encounter. Off couse we can also give
>> you some support
>> for floorplanning and other things, but usually floorplanning is
>> extremaly chip dependent
>> eapecially in mixed signal chips where the main constraint comes from
>> the analog part.
>>
>> BTW, just for curiosity, what is the application you are planning for
>> this chip?
>>
>> Cheers,
>> Davide
>>
>>
>> Il 16/06/2016 22:40, Olof Kindgren ha scritto:
>>> Hi,
>>>
>>> We're thinking of doing a mixed-signal ASIC with a simple CPU to
>>> control some aspects of the analog parts. The digital parts will
>>> consist of a CPU, memory + some GPIO, memory and probably some
>>> mechanism for loading and debugging programs (e.g. boot ROM, SPI
>>> controller, jtag+debug interface)
>>>
>>> What I wonder now is how much I can reuse from existing ASIC
>>> implementations. First example that comes to mind is Pulp/Pulpino, but
>>> there seem to have been plenty of other tapeouts, especially from
>>> academia, of OpenRISC and RISC-V systems. As I don't have very much
>>> experience of the ASIC backend flow, I'm not sure to which extent
>>> things can be reused at all. Can I reuse existing netlists, floor
>>> plans or even parts of the mask sets?
>>> _______________________________________________
>>> Discussion mailing list
>>> Discussion at lists.librecores.org
>>> https://lists.librecores.org/listinfo/discussion
>>
>>
>>
>> 5x1000 AI GIOVANI RICERCATORI
>> DELL'UNIVERSITÀ DI BOLOGNA
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5x1000 AI GIOVANI RICERCATORI
DELL'UNIVERSITÀ DI BOLOGNA
Codice Fiscale: 80007010376


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