[Librecores Discussion] Discussing EDSAC museum on FPGA for GSoC project with FOSSi
hatim at hatimak.me
Thu Mar 9 19:28:24 CET 2017
I hope this finds you well. I am Hatim, an undergraduate in my pre-final
year pursuing Bachelors in Electrical Engineering. My academic interests
lie in the computer organisation and architecture realm, and I am looking
forward to taking up higher education in the said domain. I am keenly
interested in the project titled "First-generation Museum on FPGA" with
FOSSi under GSoC. I am interested in replicating the EDSAC on an FPGA.
Over the other first-generation computers, I prefer to work on EDSAC mainly
because replicating it seems rather challenging as exhaustive documentation
on it is unavailable. It is widely known that the original team working on
the EDSAC tweaked the designs multiple times. It is this challenge at the
heart of this GSoC project that excites me!
Here are a couple of my thoughts and ideas on the project -
1. Going with a top-down approach, here is a preliminary breakdown of work
- the project will mainly involve studying the EDSAC from existing
documentation and breaking down the architecture into independent logical
subdivisions (just like the EDSAC itself is divided up into 120 panels
performing specific functions). We will then need to identify the data flow
and circuits to build abstractions through Verilog modules (for instance,
identifying that a circuit behaves like a shift register or a counter,
etc.). Once the known circuitry is mapped onto proper modules, we will have
to fill in the gaps arising out of missing documentation. This will be an
iterative process and after each cycle, we will move closer and closer to
replicating the EDSAC in its entirety. A more long-lasting task would be to
iron out the anomalies arising out of corner cases (which, IMHO, are
notorious for making themselves visible only in tests).
Please let me know your thoughts/feedback on the above approach.
2. This project aims to help hobbyists and programmers learn about the
inner workings of computers, trace our computer heritage, and to "tangibly"
see how far we have come from vacuum tube computing era to the current
supercomputing era. To this end, one of the main things we will have to
focus on is - documentation. The project will be a complete learning
resource only when we have both the code and the supporting documentation.
Over the coming days, I will continue to work on evolving (1) and (2) into
a more concrete proposal.
3. The National Museum of Computing in Bletchley Park (UK) is currently
working on reconstructing the EDSAC as it was in 1951, and should have it
operational by late 2017. TNMOC also harbours the Harwell Dekatron/WITCH,
which was rebooted in 2012. A senior of mine was working on building a
WITCH emulator written in C. Back then I got a chance to study the WITCH
and I even made some contributions to his emulator work. Those of us (like
me) who have an academic interest in computers can enjoy playing around in
the FPGA museum in lieu of visiting Bletchley Park!
4. This is an idea - how about instead of using Verilog, we use Chisel? I
like the idea of having an open-source hardware construction language
powering an open-source effort! I am experienced with Chisel only at a
basic level, but will be picking it up over the next 2-3 weeks. What do you
A little background about myself -
I am experienced with FPGAs and Verilog HDL. Under the guidance of my VLSI
Design course instructor, I am currently working on a project to prototype
the Intel 8085 microprocessor on a Xilinx Spartan-3E FPGA, using Verilog
HDL. I'll also be adding basic pipelining to the prototype in a later
stage. My objective is to investigate the performance delta due to the
addition of pipelining. I will be open-sourcing all of the code generated
as part of this project once I pass evaluation at my University. In an
earlier course, I gained exposure to developing full-custom designs and
simulating them (couldn't fabricate any design as my University does not
have the requisite equipment). If you wish to peruse my profile further,
please have a look at my LinkedIn profile , at my CV , or at my
GitHub profile . I'd be glad to answer any questions you have.
Looking forward to hearing from you and discussing things further. Will let
you know of any updates I receive from TNMOC. Thank you for your time.
Have a good day!
Undergraduate, Electrical Engineering
Indian Institute of Technology Patna
hatim at hatimak.me, hatim.ee14 at iitp.ac.in
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