[Librecores Discussion] Hello everyone & Museum on FPGA
eric.heungth at gmail.com
Thu Mar 30 15:29:56 CEST 2017
Thank you for your comments and pointing out the difficulty of implementing
a electro-mechanical devices in FPGA. FPGA is something new to me and
therefore I cannot reliably estimate the work it takes for implementation.
Considering the ultimate goal of this project "exposing these historic
computers to a new generation", I have made changes to my plan:
1, New target -> ENIAC
I will target ENIAC instead of Zuses Z3 due to the potential difficulty in
implementing electro-mechanical devices.
2, Two phased implementation
In the first phase, ENIAC will be implemented using the simple HDL language
in the "Nand2Tetris Software Suite". Based on the result, I will implement
it again in the MyStorm board in second phase.
The "Nand2Tetris Software Suite" is an open source package with a complete
accompanying open course on computer architecture designed for students
with minimal pre-requisite. By implementing it on this platform, we can
ensure the maximal target audience achievable. People who don't know FPGA,
(like me), can begin with the open course material and progress to a
complete ENIAC implementation step by step. There will be another run of
the open course "From Nand to Tetris" starting this 27 March. Therefore in
terms of schedule, I can catch up with my HDL knowledge along the course in
mean time before the summer start. Since I am a beginner in FPGA too, I
will faces the same problems other learners will face, by logging and
sharing my experience in this project, I can make the whole project more
3, Regarding mapping of I/O devices
I have been following the thread and the ideas of standardized the I/O from
Hatim is good. As he is definitely more experienced in this regard, it will
be much better for me to work with him in this part instead of me inventing
something highly restrictive. Such that, the I/O devices between difference
historical computer implemented in this project can be exchanged.
Tsz Hin Heung
On Sat, Mar 25, 2017 at 10:52 AM, Jeremy Bennett <
jeremy.bennett at embecosm.com> wrote:
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> On 24/03/17 11:26, Eric Heung wrote:
> > Hi Jeremy,
> > I have been look at a couple of historical first generation
> > computers, I am now targeting the Zuses Z3, one of the early
> > runner of computer that developed independently. Although it is not
> > in general turing complete and does not store the programme in
> > memory as data, it still resemble a lot of a modern computer. To
> > study the way Zuses Z3 evolve from a mechanical device Z1 to a
> > electro-mechanical device will be a very interest project to me
> > =D. I plan to use VHDL as it is more similar to the mini-language
> > taught in form nand to tetris and it maps closer to actual
> > hardware connections.
> Hi Eric,
> We discussed the Konrad Zuse machines when we were drawing up the
> proposals. We decided to focus on the first electronic computers.
> Whilst you can emulate electromechanical in FPGA, it seemed a very big
> Zuse was very important, but stayed with the electro-mechanical
> approach long after others had moved to valves. His first valve
> machine was the Z22 in the mid-50's and by then the transistor had
> been invented. Z22 even had an Algol 58 compiler. The Z23 was I think
> a transistor machine, and I think later versions of the Z22 were
> converted to transistors.
> However we are open to all proposals and exploring the evolution of Z1
> to Z3 is certainly interesting. Remember the objective of exposing
> these historic computers to a new generation. You'll need to address
> how you make your solution as accessible as possible.
> > I have a already found a number of sites/docs describing the inner
> > working of Z1 - Z3 (though some of the materials including the
> > original design sketch and graphs are in German which I do not
> > understand.) My current problem is I am not sure if the
> > scope/target will be too difficult for me, considering I am a
> > novice in computer architecture and VHDL.
> I think rendering electro-mechanical in FPGA will be hard - that's one
> reason why we suggested valve computers. I would hope Google Translate
> would help you with translating documentation - on the whole technical
> material translates reasonably well.
> VHDL does not have so many open source tools as Verilog, so you'll
> need to be clear about the tools you plan to use.
> > Any comment and advice would be very much appreciated =D
> Hope the above comments help.
> Best wishes,
> > Best wishes, Eric
> > On Mon, Mar 20, 2017 at 1:46 PM, Jeremy Bennett
> > <jeremy.bennett at embecosm.com <mailto:jeremy.bennett at embecosm.com>>
> > wrote:
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> > On 19/03/17 16:24, Eric Heung wrote:
> >> Hi everyone~!
> >> I'm Eric Heung, a master student currently studying in space
> >> science and technology in Kiruna, Sweden. I just stumbled upon
> >> the "Museum on FPGA" project on Google Summer of Code and it
> >> seems super interesting to me.
> >> I am always interested the computer architecture and H/W, the
> >> study of how individual electrical/electronic component works
> >> together as a "computer". Unfortunate my previous bachelor and
> >> currently master study only exposed me on the
> >> electronics/circuitry realm and the computer programming realm,
> >> leaving the bridge between H/W and S/W untouched. The project
> >> "Museum on FPGA" looks like an excellent start for me to get
> >> hands on both FPGA and computer architecture. I have no official
> >> exposure on the FPGA or related hardware architecture, except
> >> the wonderful course "From Nand to Tetris" offered by Coursera.
> >> Therefore any help from the community would be very much
> >> appreciated.
> >> I know I have already missed the "discussion phase" (February 27
> >> - March 20) of the project but I would still love to get
> >> involved in this project, no matter in form of Google Summer of
> >> Code or as a personal summer project. May I ask how should I get
> >> started and do I need to buy a FPGA development board for it? And
> >> if so which model should I purchase?
> > Hi Eric,
> > You need to work up your ideas - feel free to discuss them here.
> > Then make an application through the GSoC website and you'll be
> > compared with all the others. We are looking for each applicant to
> > bring their own ideas to the table on this.
> > I would expect the mentors to make a suitable FPGA board available
> > to any student who is accepted for this project. Our suggestion is
> > the MyStorm board.
> > Best wishes,
> > Jeremy
> > - -- Tel: +44 (1590) 610184 <tel:%2B44%20%281590%29%20610184>
> > Cell: +44 (7970) 676050 <tel:%2B44%20%287970%29%20676050>
> > SkypeID: jeremybennett Twitter: @jeremypbennett Email:
> > jeremy.bennett at embecosm.com <mailto:jeremy.bennett at embecosm.com>
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