[Librecores Discussion] [GSoC2017] Integration of a RISC V CPU on LimeSDR project
xfguo at xfguo.org
Fri May 26 14:21:53 CEST 2017
Why rocket-chip did not in you list? The RoCC will support adding DSP acceleration instructions which is better for wireless communication applications.
> 在 2017年5月26日，下午7:01，Cairo Caplan <cairorj at gmail.com> 写道：
> My name is Cairo, and I am very happy to be working on the port/integration of RISC V CPUs to the LimeSDR gateware. I am a brazilian PhD student at Aix-Marseille university. For long I have interest to work with a open source CPU project and I find amazing the concept of SDR in hardware.
> The objective of this project is to replace the current closed source NIOS II CPU present on the gateware with a RISC V CPU.
> I picked the following three flavors of open sources RISC V CPUs that are FPGA friendly to test, which I want to profit as they can share the same Instructions Set and software tools.
> Orca - https://github.com/VectorBlox/orca ,
> Pulpino - https://github.com/pulp-platform/pulpino/tree/master/fpga
> picorv32 - https://github.com/cliffordwolf/picorv32
> As soon as I get the first of them working my focus will turn on how to make the system FuseSoC friendly.
> My work will be available on the riscv branch of LimeSDR Gateware repository on GitHub -
> https://github.com/myriadrf/LimeSDR-USB_GW/tree/riscv ,
> on the MyriadRF Wiki - https://wiki.myriadrf.org/LimeSDR-USB_RISC-V and on a blog which I am going to release soon, relating my experiences.
> You can contact me at cairorj at gmail com , I am open to suggestions and advices.
> Thank you
> Kind Regards, Cairo Caplan
> Discussion mailing list
> Discussion at lists.librecores.org
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