[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?

Hatim Kanchwala hatim at hatimak.me
Tue May 30 12:32:34 CEST 2017


Hello,

Could someone please recommend what coding style for Verilog I can follow for my EDSAC FPGA Museum project? My experience is limited to a sandbox environment of University courses and labs. I'd like to know what standards do Verilog developers follow for real-world projects?

My mentor, Jeremy, suggested I write to the mailing list requesting for your recommendations. Thank you for your time!

Hatim

—
https://hatimak.me
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