[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?
hatim at hatimak.me
Tue May 30 12:32:34 CEST 2017
Could someone please recommend what coding style for Verilog I can follow for my EDSAC FPGA Museum project? My experience is limited to a sandbox environment of University courses and labs. I'd like to know what standards do Verilog developers follow for real-world projects?
My mentor, Jeremy, suggested I write to the mailing list requesting for your recommendations. Thank you for your time!
-------------- next part --------------
A non-text attachment was scrubbed...
Size: 801 bytes
Desc: Message signed with OpenPGP
More information about the Discussion