[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?
jamey.hicks at gmail.com
Tue May 30 14:42:32 CEST 2017
I also recommend using verilator lint and to edit your code so that there
are no warnings.
On Tue, May 30, 2017 at 8:17 AM Jeremy Bennett <jeremy.bennett at embecosm.com>
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> On 30/05/17 11:32, Hatim Kanchwala wrote:
> > Hello,
> > Could someone please recommend what coding style for Verilog I can
> > follow for my EDSAC FPGA Museum project? My experience is limited
> > to a sandbox environment of University courses and labs. I'd like
> > to know what standards do Verilog developers follow for real-world
> > projects?
> > My mentor, Jeremy, suggested I write to the mailing list requesting
> > for your recommendations. Thank you for your time!
> Hi all,
> I'm a software engineer, so not well qualified to advise Hatim.
> The best I can suggest is for layout use the emacs verilog-mode style
> (3 space indentation) and for implementation:
> - - use blocking assignment in combinatorial always blocks
> - - use non-blocking assignment in sequential always blocks
> - - register outputs, not inputs
> - - use Verilator's linting to get feedback.
> Advice from professionals much appreciated.
> Best wishes,
> > Hatim
> > — https://hatimak.me
> - --
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