[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?

Stefan Wallentowitz stefan at wallentowitz.de
Tue May 30 14:49:48 CEST 2017


Hi Hatim,

generally, the papers of Stuart Sutherland are a good read for things
like best practices: http://www.sutherland-hdl.com/papers.html

I think System Verilog support in Yosys is pretty limited. I would
suggest having a look which constructs are allowed and then check with
this paper:
http://www.sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf

If there is a good support for the recommendations, it is definitely
worth giving it a shot.

Beyond that I have a lot of personally favored styling, for example
about how to arrange your code, but as I am close to the project I will
probably point out directly when I think some code could be written
better (functionally or for readability).

Cheers,
Stefan

On 30.05.2017 12:32, Hatim Kanchwala wrote:
> Hello,
> 
> Could someone please recommend what coding style for Verilog I can follow for my EDSAC FPGA Museum project? My experience is limited to a sandbox environment of University courses and labs. I'd like to know what standards do Verilog developers follow for real-world projects?
> 
> My mentor, Jeremy, suggested I write to the mailing list requesting for your recommendations. Thank you for your time!
> 
> Hatim


-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: OpenPGP digital signature
URL: <http://lists.librecores.org/pipermail/discussion/attachments/20170530/e2eeffcd/attachment.sig>


More information about the Discussion mailing list