[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?

Matt P. Dziubinski matdzb at gmail.com
Tue May 30 15:12:27 CEST 2017


One more resource which may be of use: OH! Open Hardware for Chip 
Designers - Silicon proven Verilog library for IC and FPGA designers

I've found the aforementioned papers by Stuart Sutherland pretty 
informative indeed -- as well as the ones by Cliff Cummings and Don Mills.
I've collected some of these resources here -- perhaps this will be of 
some use:

On a more basic level, the following source offers a good explanation of 
the best practice of using blocking assignments for combinational logic 
(`=` & `always_comb`) vs. nonblocking assignments for sequential logic 
(`<=` & `always_ff`): Appendix A "Hardware Description Languages" from 
Neil Weste, David Harris (2010) "CMOS VLSI Design: A Circuits and 
Systems Perspective" (4th Edition)

As one data point, I was being able to synthesize designs in 
SystemVerilog (for an iCE40 FPGA) using `always_comb` and `always_ff` 
with Yosys.



On 5/30/2017 14:49, Stefan Wallentowitz wrote:
> Hi Hatim,
> generally, the papers of Stuart Sutherland are a good read for things
> like best practices: http://www.sutherland-hdl.com/papers.html
> I think System Verilog support in Yosys is pretty limited. I would
> suggest having a look which constructs are allowed and then check with
> this paper:
> http://www.sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf
> If there is a good support for the recommendations, it is definitely
> worth giving it a shot.
> Beyond that I have a lot of personally favored styling, for example
> about how to arrange your code, but as I am close to the project I will
> probably point out directly when I think some code could be written
> better (functionally or for readability).
> Cheers,
> Stefan
> On 30.05.2017 12:32, Hatim Kanchwala wrote:
>> Hello,
>> Could someone please recommend what coding style for Verilog I can follow for my EDSAC FPGA Museum project? My experience is limited to a sandbox environment of University courses and labs. I'd like to know what standards do Verilog developers follow for real-world projects?
>> My mentor, Jeremy, suggested I write to the mailing list requesting for your recommendations. Thank you for your time!
>> Hatim
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