[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?

[Stefan Wallentowitz]

On 30.05.2017 15:12, Matt P. Dziubinski wrote:

> One more resource which may be of use: OH! Open Hardware for Chip
> Designers - Silicon proven Verilog library for IC and FPGA designers
> https://github.com/parallella/oh
> https://github.com/parallella/oh#design-guide
> https://github.com/parallella/oh#coding-guide

Those indeed have many good points.

Just out of curiosity, is there anyone aware of a generic
approach/framework to verify coding guidelines? I know many software
projects have such things, are they hacked together or something
established and reusable? Also giving guidance and not only
matched/error would be interesting.

Cheers,
Stefan

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