[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?

Stefan Wallentowitz stefan at wallentowitz.de
Tue May 30 15:22:26 CEST 2017

On 30.05.2017 15:12, Matt P. Dziubinski wrote:

> One more resource which may be of use: OH! Open Hardware for Chip
> Designers - Silicon proven Verilog library for IC and FPGA designers
> https://github.com/parallella/oh
> https://github.com/parallella/oh#design-guide
> https://github.com/parallella/oh#coding-guide

Those indeed have many good points.

Just out of curiosity, is there anyone aware of a generic
approach/framework to verify coding guidelines? I know many software
projects have such things, are they hacked together or something
established and reusable? Also giving guidance and not only
matched/error would be interesting.


-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: OpenPGP digital signature
URL: <http://lists.librecores.org/pipermail/discussion/attachments/20170530/ed032c63/attachment.sig>

More information about the Discussion mailing list