[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?

Philipp Wagner lists at philipp-wagner.com
Tue May 30 15:25:02 CEST 2017

On 05/30/2017 03:22 PM, Stefan Wallentowitz wrote:
> On 30.05.2017 15:12, Matt P. Dziubinski wrote:
>> One more resource which may be of use: OH! Open Hardware for Chip
>> Designers - Silicon proven Verilog library for IC and FPGA designers
>> https://github.com/parallella/oh
>> https://github.com/parallella/oh#design-guide
>> https://github.com/parallella/oh#coding-guide
> Those indeed have many good points.
> Just out of curiosity, is there anyone aware of a generic
> approach/framework to verify coding guidelines? I know many software
> projects have such things, are they hacked together or something
> established and reusable? Also giving guidance and not only
> matched/error would be interesting.

SpyGlass (now Synopsys) and RealIntent Ascent should be the two major 
ones in this area. I don't think there are open sources solutions apart 
from basic linting as supported by Verilator.


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