[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?

Martin d'Anjou martin.danjou14 at gmail.com
Tue May 30 15:52:52 CEST 2017


On 17-05-30 09:22 AM, Stefan Wallentowitz wrote:
> On 30.05.2017 15:12, Matt P. Dziubinski wrote:
>
>> One more resource which may be of use: OH! Open Hardware for Chip
>> Designers - Silicon proven Verilog library for IC and FPGA designers
>> https://github.com/parallella/oh
>> https://github.com/parallella/oh#design-guide
>> https://github.com/parallella/oh#coding-guide
> Those indeed have many good points.
>
> Just out of curiosity, is there anyone aware of a generic
> approach/framework to verify coding guidelines? I know many software
> projects have such things, are they hacked together or something
> established and reusable? Also giving guidance and not only
> matched/error would be interesting.

I spend more time reading code than writing it, so to me it is about
making code readable to the point that bugs literally stand out. This
include formatting and layout, naming conventions, general rules for the
various language constructs, and small and big patterns (e.g. early
returns or factory).

I find it useful to distinguish between language coding guidelines (e.g.
SystemVerilog, VHDL), and framework coding guidelines (e.g. UVM).

This particular coding guideline has helped me write more readable
programs in multiple languages:
http://geosoft.no/development/javastyle.html

I never bothered translating it to SV though.

Martin


-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 490 bytes
Desc: OpenPGP digital signature
URL: <http://lists.librecores.org/pipermail/discussion/attachments/20170530/47742554/attachment.sig>


More information about the Discussion mailing list