[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?

Roland Lutz rlutz at hedmen.org
Tue May 30 16:20:39 CEST 2017

On Tue, 30 May 2017, Martin d'Anjou wrote:
> I spend more time reading code than writing it, so to me it is about 
> making code readable to the point that bugs literally stand out.

For C code, I found the Linux kernel coding style has precisely this 
effect, so I try to follow it as much as reasonable:


I'm not sure how this applies to Verilog, though.


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