[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?

Richard Herveille richard.herveille at roalogic.com
Tue May 30 15:32:14 CEST 2017

BluePearl Software (www.bluepearlsoftware.com) provides a combined linter, cdc, sdc, fsm, and clocking checker.
It’s what we use.


Richard Herveille
Managing Director
Phone +31 (45) 405 5681
Cell +31 (6) 5207 2230
richard.herveille at roalogic.com <mailto:richard.herveille at roalogic.com>

> On 30 May 2017, at 15:25, Philipp Wagner <lists at philipp-wagner.com> wrote:
> On 05/30/2017 03:22 PM, Stefan Wallentowitz wrote:
>> On 30.05.2017 15:12, Matt P. Dziubinski wrote:
>>> One more resource which may be of use: OH! Open Hardware for Chip
>>> Designers - Silicon proven Verilog library for IC and FPGA designers
>>> https://github.com/parallella/oh
>>> https://github.com/parallella/oh#design-guide
>>> https://github.com/parallella/oh#coding-guide
>> Those indeed have many good points.
>> Just out of curiosity, is there anyone aware of a generic
>> approach/framework to verify coding guidelines? I know many software
>> projects have such things, are they hacked together or something
>> established and reusable? Also giving guidance and not only
>> matched/error would be interesting.
> SpyGlass (now Synopsys) and RealIntent Ascent should be the two major ones in this area. I don't think there are open sources solutions apart from basic linting as supported by Verilator.
> Philipp
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