[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?

Richard Herveille richard.herveille at roalogic.com
Tue May 30 16:54:54 CEST 2017


I read through the link you provided. Even though I agree with the general ideas, it’s not applicable to Verilog as much.

Richard




Richard Herveille
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richard.herveille at roalogic.com <mailto:richard.herveille at roalogic.com>





> On 30 May 2017, at 16:20, Roland Lutz <rlutz at hedmen.org> wrote:
> 
> On Tue, 30 May 2017, Martin d'Anjou wrote:
>> I spend more time reading code than writing it, so to me it is about making code readable to the point that bugs literally stand out.
> 
> For C code, I found the Linux kernel coding style has precisely this effect, so I try to follow it as much as reasonable:
> 
> https://www.kernel.org/doc/html/v4.10/process/coding-style.html
> 
> I'm not sure how this applies to Verilog, though.
> 
> Roland
> 
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