[Librecores Discussion] [GSoC2017] What are your Verilog coding recommendations?
lists at philipp-wagner.com
Wed May 31 10:00:20 CEST 2017
On 05/31/2017 04:49 AM, Martin d'Anjou wrote:
> On 17-05-30 02:33 PM, Amitosh Swain Mahapatra wrote:
>> ANTLR used to bundle a Verilog grammar, but I cannot find it at the
> I think it was written for ANTLR 1 or 2, which I would never use: ANTLR
> 4 is way better than its predecessors.
> Recently I ran across these two SystemVerilog repositories, the first
> one seems more active:
> * https://github.com/MikePopoloski/slang
> * https://github.com/svstuff/systemverilog
SystemVerilog is a insanely complex language. From my experience, as of
today the only really usable parser is the one from Verilator, also
available through its Verilog-Perl module.
I did test the other two you mentioned here a couple months back with
designs we use around here (with very limited use of newer SV features,
as all these design synthesize correctly in Vivado and Verilator), and
both had some issues which caused them to fail parsing. I unfortunately
don't have the exact details around at the moment to be more specific.
However, for linting and code checking a "standard" parser isn't
sufficient. As checking for "code style" goes, the parser shouldn't
disregard things like whitespace and other formatting. And as parsing
for syntax errors goes, useful error messages rarely come out of
standard errors provided by a parser generator.
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