[Librecores Discussion] pinmux gsoc2018 proposal

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jan 23 01:51:56 CET 2018


hi,

saw the risc-v hw-dev ping, thought "ah ha!" now might be a good time
to propose working towards this:
http://rhombus-tech.net/riscv/shakti/m_class/pinouts/

the problem: you can't fit all the hard macros for all possible
functions onto a single chip for all possible purposes to which an
[arbitrary] SoC would be put... because it would be an insanely
expensive 1500 pin monster with 80% of its pinouts totally wasted.

the solution: a pinmux.

question: does such a pinmux exist as a libre licensed hard macro?
answer: no.

question: does a general-purpose GPIO hard macro exist with an
"alternative function" option?
answer: yes.  on opencores.

question: does it help?
answer: no it doesn't.  a single "alternative function" is not enough.
to conserve pins you need at least *three* alternative functions and
some TI OMAP SoCs even have *seven*.

question: how many libre SoC projects would a pinmux benefit?
answer: all of them.  RISC-V, ZipCPU, OR1x, absolutely all of them
right from the lowliest 8-bit 8mhz core all the way to 16-SMP 2.5ghz
RISC-V monsters.

the proposal may be broken down into a series of tasks, creating the
building blocks that could be used to work their way up towards
something like the above

* create the basic single-pin 4-way (or N-way) I/O multiplexer with
register-controllable pullup and pulldown and also register-controlled
hot-swapping between Open Drain and Push-Push CMOS output modes.  this
is basically exactly what ST, Atmel etc. etc. have.  it's not rocket
science, and it's really quite straightforward.  total amount of VHDL:
well under 200 lines.

* get that working stand-alone

* get RISC-V up and running (doesn't matter which one: any one which
is stable even if it's old).  lowRISC eth-0.5 branch would probably be
a good start as they have sd/mmc and ethernet already up and running.
time will be of the essence here, it's not *actually* the main focus
of the proposal, so even ZipCPU, OR1k or... *anything* that's easy to
get up and running FAST (but also preferably has a linux kernel port)
is preferable.

* look for a suitable linux kernel driver and drop it on top of a bank
of the above pinmuxes.  celebrate if it works

* IF THERE IS TIME start adding extra functions such as UART, PWM,
I2C, SPI, SD/MMC and so on.

* *DOCUMENT* the process of how to add multiple banks of pinmuxes

* *DOCUMENT* how to add new functions behind each bank.

if the student gets as far as adding several different functions, they
will need some sort of adafruit or other breakout board(s) to be
connected to an FPGA development system, with an XC105 and a wiring
loom to connect different peripherals in turn to the exact same pins,
in order to demonstrate that it's working.


this proposal does not just benefit one processor core, it benefits
*all* processor cores.  there simply does not exist a pinmux right now
because most libre projects are either extremely specialist (a few
dedicated hard macros) or they are primarily designed as an exercise
in developing a core.... not an actual processor.

i genuinely do not know why it has not occurred to anyone in the libre
silicon community to design a pinmux, but one is definitely,
definitely needed.

l.

---
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