[Librecores Discussion] [GSoC2018][Improve the LibreCores.org in terms of discoverability] Proposal

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Jul 21 17:21:38 CEST 2018

On Friday, March 30, 2018, Richard Herveille <richard.herveille at roalogic.com>

> Hi Luke,
> If you know how to write concurrent C, you almost know how to write
> Verilog. I can get you up to speed in a day or two.
Cool. I am getting there, it is slowly sinking in.

> Otherwise I suggest MyHDL.
Yeah i have tried myhdl it is a pain, only a strict subset of python can be
used. It is ok, i will manage.

Right now I am in chennai at the RISE  Lab, expanding the pinmux to an
interface autogenerator, creating instances of peripherals and integrating
them onto an AXIlite bus.  I want to get as much of that done as possible.

I2c spi quadspi eint uart quart pwm gpio are all in.

TODO is RGMII VGALCD FlexBus UTMI/ULPI these are all hi speed and almost
certainly need to go on a fast bus. Some need wishbone conversion.  If
anyone knows how to convert alex forencich's gmii to rgmii that would be
real handy

>From august i need to change focus, so if the team in chennai are able to
work independently that is good.

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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