[Librecores Discussion] [gsoc] status of SystemVerilog Preprocessor

Martin d'Anjou martin.danjou14 at gmail.com
Sat Mar 2 03:53:52 CET 2019


Hello,

Thanks for your interest in the project. Sadly, I do not have time to
mentor the SystemVerilog Preprocessor project unless we find one or two
"main" mentors for it, leaving the role of a "part time" mentor. This is
because I am an Org Admin and mentor on the Jenkins project already.

Let me know if a mentor is found, I hope someone in the Librecores can help
you. CC librecores.

Best,
Martin d'Anjou
Jenkins GSoC Org Admin

On Fri, Mar 1, 2019 at 3:12 AM IMT2016083 Srinivasan Vijayraghavan <
Srinivasan.Vijayraghavan at iiitb.org> wrote:

> Hi Mr. Martin Danjou,
>
> I'm a student from IIITB, India. I'm pursuing my undergrad in Computer
> Science and I'm currently in my junior year.
>
> I found this
> <https://fossi-foundation.org/gsoc18-ideas#a-systemverilog-preprocessor>
> (A SystemVerilog Preprocessor) listing from the gsoc '18 ideas page to be
> interesting, and something which I can work on. On gsoc's official page
> <https://summerofcode.withgoogle.com/archive/2018/organizations/6276259533291520/#projects>
> (list of completed projects), this particular project hasn't been listed.
>
> I would like to know the current status of this project (if it's available
> ) and if you're free to mentor, we could discuss further.
>
> Thanks and Regards
> S Vijayraghavan (VJ)
> Github: rinz13r <https://github.com/rinz13r>
>
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