[Librecores Discussion] [gsoc] status of SystemVerilog Preprocessor
jeremy.bennett at embecosm.com
Wed Mar 6 17:56:43 CET 2019
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On 02/03/19 02:53, Martin d'Anjou wrote:
> Thanks for your interest in the project. Sadly, I do not have time
> to mentor the SystemVerilog Preprocessor project unless we find one
> or two "main" mentors for it, leaving the role of a "part time"
> mentor. This is because I am an Org Admin and mentor on the Jenkins
> project already.
> Let me know if a mentor is found, I hope someone in the Librecores
> can help you. CC librecores.
I've offered to help with mentoring, and given the subject area I
might be qualified. Are you able to flesh out your thoughts on the
project any further?
> Best, Martin d'Anjou Jenkins GSoC Org Admin
> On Fri, Mar 1, 2019 at 3:12 AM IMT2016083 Srinivasan Vijayraghavan
> <Srinivasan.Vijayraghavan at iiitb.org
> <mailto:Srinivasan.Vijayraghavan at iiitb.org>> wrote:
> Hi Mr. Martin Danjou,
> I'm a student from IIITB, India. I'm pursuing my undergrad in
> Computer Science and I'm currently in my junior year.
> I found this
(A SystemVerilog Preprocessor) listing from the gsoc '18 ideas page
> to be interesting, and something which I can work on. On gsoc's
> official page
(list of completed projects), this particular project hasn't been
> I would like to know the current status of this project (if it's
> available ) and if you're free to mentor, we could discuss
> Thanks and Regards S Vijayraghavan (VJ) Github: rinz13r
> _______________________________________________ Discussion mailing
> list Discussion at lists.librecores.org
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Email: jeremy.bennett at embecosm.com
PGP key: 1024D/BEF58172FB4754E1 2009-03-20
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