[Librecores Discussion] [gsoc] status of SystemVerilog Preprocessor
martin.danjou14 at gmail.com
Fri Mar 8 06:53:31 CET 2019
>> Are you able to flesh out your thoughts on the
>> project any further?
This project, the way I envisioned it, is the first part of a bigger
project that would consist of the pre-processor, a lexer, a parser, and a
family of tree walkers, the way ANTLR means it to be.
However, SV is hard to preprocess in ANTLR 1) because Verilog/SystemVerilog
was created with the C preprocessor in mind; and 2) because ANTLR pays
little to no considerations to the pre-processing problem. ANTLR does not
aim to solve the preprocessing problem because that problem has already
been "solved" in the general sense: CPP exists. So to have a preprocessor
with an ANTLR project means to implement it independently outside of ANTLR,
or all within the lexer but with no help from ANTLR iself (other than what
the implementation language provides). If a preprocessor front end could be
written, then the rest of the "compiler" chain can be written leveraging
Someone claims to have written a C Preprocessor in ANTLR, but the glue code
is missing. It could be used as inspiration:
There is a solo project in fairly advanced state called "slang" by Mike
Popoloski. It has as Preprocessor.cpp
Maybe instead of starting from scratch it would be worth contacting the
owner to see if he's interested in GSoC.
At some point, Mike Lischke offered this project which contains the logic
for dealing with preprocessor conditional directives (download the bundle
and look for a file called Preprocessor.java):
Searching the ANTLR mailing list reveals a few interesting threads:
I never got very far beyond that.
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