[Embench] interrupt latency - reference results

Ofer Shinaar Ofer.Shinaar at wdc.com
Tue Apr 13 10:40:33 CEST 2021


On 12/04/2021 19:54, Jeremy Bennett wrote:

On 01/04/2021 10:46, Ronen Haen wrote:


Hi All,

      With the embench-iot <https://github.com/embench/embench-iot><https://github.com/embench/embench-iot>, all
      new results are produced in reference to the results from Arm
      Cortex M4 CPU.

      However, with embench-rt
      <https://github.com/embench/embench-rt><https://github.com/embench/embench-rt>there are no reference
      results yet.

      How should we publish results for embench-rt
      <https://github.com/embench/embench-rt><https://github.com/embench/embench-rt>?



Hi Ronen,

A good question, and as project leads, we would look to you and Ofer to
suggest the best approach.

We chose Cortex M4 as the baseline for Embench IoT, because it was a
processor widely available in a low-cost board.  I suggest a similar
approach would be good for Embench RT.

We can discuss this at next Monday's meeting.

HTH,


Jeremy

Hi Jeremy,

Since we don't have access to CM4 I think we need a mitigation solution.

If someone on the Embench group can take the test and run it on CM4 we will be more than

happy to help integrate it (if problems will pop out).

In the meantime, I suggested that SweRV will be the reference. It runs on Nexys A7<https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/> platform (not expansive)

with full FW-Infrastructure support, open-source by WD/CHIPS-Alliance.


I agree; lets put it on the agenda for the next meeting.


Thanks,

Ofer










      Thanks,


      Ronen















--

Ofer Shinaar
Senior Manager, R&D Engineering – Firmware & Toolchain, CTO Group

Western Digital®

Israel, Migdal Tefen 24959, P.O Box 3
Email: Ofer.shinaar at wdc.com<mailto:Ofer.shinaar at wdc.com>
Office: +972-4-9078783
Mobile: +972-52-2836160
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