October 2017 Archives by thread

• Messages sorted by: [ subject ] [ author ] [ date ]
• More info on this list...

Starting: Thu Oct 5 15:49:06 CEST 2017
Ending: Tue Oct 31 15:06:21 CET 2017
Messages: 99

• [OpenRISC] [PATCH v5 0/6] sim port for OpenRISC   Stafford Horne
  • [OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])   Stafford Horne
    • [OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])   Simon Marchi
      • [OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])   Stafford Horne
      • [OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])   Simon Marchi
    • [OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])   Doug Evans
    • [OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])   Doug Evans
  • [OpenRISC] [PATCH v5 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u])   Stafford Horne
    • [OpenRISC] [PATCH v5 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u])   Simon Marchi
      • [OpenRISC] [PATCH v5 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u])   Stafford Horne
    • [OpenRISC] [PATCH v5 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u])   Doug Evans
  • [OpenRISC] [PATCH v5 3/6] sim: or1k: add or1k target to sim   Stafford Horne
    • [OpenRISC] [PATCH v5 3/6] sim: or1k: add or1k target to sim   Simon Marchi
      • [OpenRISC] [PATCH v5 3/6] sim: or1k: add or1k target to sim   Stafford Horne
      • [OpenRISC] [PATCH v5 3/6] sim: or1k: add or1k target to sim   Simon Marchi
    • [OpenRISC] [PATCH v5 3/6] sim: or1k: add or1k target to sim   Doug Evans
      • [OpenRISC] [PATCH v5 3/6] sim: or1k: add or1k target to sim   Stafford Horne
  • [OpenRISC] [PATCH v5 4/6] sim: or1k: add cgen generated files   Stafford Horne
  • [OpenRISC] [PATCH v5 5/6] sim: or1k: add autoconf generated files   Stafford Horne
  • [OpenRISC] [PATCH v5 6/6] sim: testsuite: add testsuite for or1k sim   Stafford Horne
  • [OpenRISC] [PATCH v5 0/6] sim port for OpenRISC   Stafford Horne
  • [OpenRISC] [PATCH v5 0/6] sim port for OpenRISC   Stafford Horne
  • [OpenRISC] [PATCH v5 0/6] sim port for OpenRISC   Doug Evans
• [OpenRISC] [PATCH 0/5] OpenRISC SMP Support   Stafford Horne
• [OpenRISC] OpenRISC Specification updates for Multicore   Stafford Horne
• [OpenRISC] [Qemu-devel] [PATCH 2/5] target/openrisc: Make coreid and numcores configurable in state   Richard Henderson
• [OpenRISC] [Qemu-devel] [PATCH 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)   Richard Henderson
• [OpenRISC] [Qemu-devel] [PATCH 3/5] openrisc/cputimer: Perparation for Multicore   Richard Henderson
• [OpenRISC] [Qemu-devel] [PATCH 4/5] openrisc: Initial SMP support   Richard Henderson
• [OpenRISC] [Qemu-devel] [PATCH 5/5] openrisc: Only kick cpu on timeout, not on update   Richard Henderson
• [OpenRISC] [PATCH v6 0/6] sim port for OpenRISC   Stafford Horne
  • [OpenRISC] [PATCH v6 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])   Stafford Horne
    • [OpenRISC] [PATCH v6 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])   Doug Evans
  • [OpenRISC] [PATCH v6 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u])   Stafford Horne
    • [OpenRISC] [PATCH v6 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u])   Doug Evans
  • [OpenRISC] [PATCH v6 3/6] sim: or1k: add or1k target to sim   Stafford Horne
    • [OpenRISC] [PATCH v6 3/6] sim: or1k: add or1k target to sim   Doug Evans
  • [OpenRISC] [PATCH v6 4/6] sim: or1k: add cgen generated files   Stafford Horne
    • [OpenRISC] [PATCH v6 4/6] sim: or1k: add cgen generated files   Doug Evans
    • [OpenRISC] [PATCH v6 4/6] sim: or1k: add cgen generated files   Stafford Horne
  • [OpenRISC] [PATCH v6 5/6] sim: or1k: add autoconf generated files   Stafford Horne
    • [OpenRISC] [PATCH v6 5/6] sim: or1k: add autoconf generated files   Doug Evans
  • [OpenRISC] [PATCH v6 6/6] sim: testsuite: add testsuite for or1k sim   Stafford Horne
    • [OpenRISC] [PATCH v6 6/6] sim: testsuite: add testsuite for or1k sim   Doug Evans
    • [OpenRISC] [PATCH v6 6/6] sim: testsuite: add testsuite for or1k sim   Stafford Horne
      • [OpenRISC] [PATCH v6 6/6] sim: testsuite: add testsuite for or1k sim   Doug Evans
  • [OpenRISC] [PATCH v6 0/6] sim port for OpenRISC   Stafford Horne
  • [OpenRISC] [PATCH v6 0/6] sim port for OpenRISC   Doug Evans
• [OpenRISC] [PATCH v2 0/5] OpenRISC SMP Support   Stafford Horne
  • [OpenRISC] [PATCH v2 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)   Stafford Horne
  • [OpenRISC] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable   Stafford Horne
    • [OpenRISC] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable   Richard Henderson
    • [OpenRISC] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable   Stafford Horne
  • [OpenRISC] [PATCH v2 3/5] openrisc/cputimer: Perparation for Multicore   Stafford Horne
  • [OpenRISC] [PATCH v2 4/5] openrisc: Initial SMP support   Stafford Horne
  • [OpenRISC] [PATCH v2 5/5] openrisc: Only kick cpu on timeout, not on update   Stafford Horne
• [OpenRISC] [linux-litex] Linux early_printk on Arty!   Stafford Horne
• [OpenRISC] [PATCH v2] openrisc: dts: or1ksim: Add stdout-path   Stafford Horne
• [OpenRISC] [PATCH 0/3] OpenRISC doc updates   Stafford Horne
  • [OpenRISC] [PATCH 1/3] Documentation: Move OpenRISC docs out of arch/   Stafford Horne
  • [OpenRISC] [PATCH 2/3] Documentation: openrisc: Updates to README   Stafford Horne
  • [OpenRISC] [PATCH 3/3] openrisc: dts: Add OpenRISC platform SoC   Stafford Horne
    • [OpenRISC] [PATCH 3/3] openrisc: dts: Add OpenRISC platform SoC   Rob Herring
    • [OpenRISC] [PATCH 3/3] openrisc: dts: Add OpenRISC platform SoC   Stafford Horne
• [OpenRISC] [PATCH v3 00/13] OpenRISC SMP Support   Stafford Horne
  • [OpenRISC] [PATCH v3 01/13] openrisc: use shadow registers to save regs on exception   Stafford Horne
  • [OpenRISC] [PATCH v3 02/13] openrisc: add 1 and 2 byte cmpxchg support   Stafford Horne
  • [OpenRISC] [PATCH v3 03/13] openrisc: use qspinlocks and qrwlocks   Stafford Horne
  • [OpenRISC] [PATCH v3 04/13] dt-bindings: add openrisc to vendor prefixes list   Stafford Horne
  • [OpenRISC] [PATCH v3 05/13] irqchip: add initial support for ompic   Stafford Horne
    • [OpenRISC] [PATCH v3 05/13] irqchip: add initial support for ompic   Marc Zyngier
      • [OpenRISC] [PATCH v3 05/13] irqchip: add initial support for ompic   Stafford Horne
    • [OpenRISC] [PATCH v3 05/13] irqchip: add initial support for ompic   Rob Herring
  • [OpenRISC] [PATCH v3 06/13] openrisc: initial SMP support   Stafford Horne
  • [OpenRISC] [PATCH v3 07/13] openrisc: fix initial preempt state for secondary cpu tasks   Stafford Horne
  • [OpenRISC] [PATCH v3 08/13] openrisc: sleep instead of spin on secondary wait   Stafford Horne
  • [OpenRISC] [PATCH v3 09/13] openrisc: add cacheflush support to fix icache aliasing   Stafford Horne
  • [OpenRISC] [PATCH v3 10/13] openrisc: add simple_smp dts and defconfig for simulators   Stafford Horne
  • [OpenRISC] [PATCH v3 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT   Stafford Horne
  • [OpenRISC] [PATCH v3 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing   Stafford Horne
  • [OpenRISC] [PATCH v3 13/13] openrisc: add tick timer multi-core sync logic   Stafford Horne
• [OpenRISC] OpenRISC Architecture 1.2   Stafford Horne
  • [OpenRISC] OpenRISC Architecture 1.2   Olof Kindgren
• [OpenRISC] [PATCH v4 01/13] openrisc: use shadow registers to save regs on exception   Stafford Horne
• [OpenRISC] [PATCH v4 02/13] openrisc: add 1 and 2 byte cmpxchg support   Stafford Horne
• [OpenRISC] [PATCH v4 03/13] openrisc: use qspinlocks and qrwlocks   Stafford Horne
• [OpenRISC] [PATCH v4 05/13] irqchip: add initial support for ompic   Stafford Horne
  • [OpenRISC] [PATCH v4 05/13] irqchip: add initial support for ompic   Marc Zyngier
    • [OpenRISC] [PATCH v4 05/13] irqchip: add initial support for ompic   Stafford Horne
      • [OpenRISC] [PATCH v4 05/13] irqchip: add initial support for ompic   Marc Zyngier
• [OpenRISC] [PATCH v4 06/13] openrisc: initial SMP support   Stafford Horne
• [OpenRISC] [PATCH v4 07/13] openrisc: fix initial preempt state for secondary cpu tasks   Stafford Horne
• [OpenRISC] [PATCH v4 08/13] openrisc: sleep instead of spin on secondary wait   Stafford Horne
• [OpenRISC] [PATCH v4 09/13] openrisc: add cacheflush support to fix icache aliasing   Stafford Horne
• [OpenRISC] [PATCH v4 10/13] openrisc: add simple_smp dts and defconfig for simulators   Stafford Horne
• [OpenRISC] [PATCH v4 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT   Stafford Horne
• [OpenRISC] [PATCH v4 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing   Stafford Horne
• [OpenRISC] [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic   Stafford Horne
  • [OpenRISC] [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic   Matt Redfearn

Last message date: Tue Oct 31 15:06:21 CET 2017
Archived on: Thu Nov 2 14:05:14 CET 2017

• Messages sorted by: [ subject ] [ author ] [ date ]
• More info on this list...