[Open SoC Debug] Status JTAG debug controller

Richard Herveille Richard.Herveille at roalogic.com
Wed Dec 2 20:41:28 CET 2015

Just wanted to let you know the code at https://github.com/RoaLogic/adv_dbg_if is useable clean. Both wishbone and AHB pass the basic system testbench. 
I am working on the debug memory map at the moment. I sent some feedback to Andreas already. Ideas and feedback are welcome. 


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