[Open SoC Debug] MMIO-Interface

Stefan Wallentowitz stefan at wallentowitz.de
Tue Nov 17 14:45:59 CET 2015


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Hi Andreas,

I will join three parallel mail thread into this mailing list
discussion (which is between us two at the moment..).

Will copy open discussion points below.

 * Bursts on the MMIO Interface: You are right they are not needed as
we provide single-cycle accesses. mmio_bridge has them on the input
side as the debug packets can be bursts, but that should be handled
internally. Removed on the MMIO Interface [1].

 * Naming conventions: You rightly noted that the naming should be
better, hence we use the valid/ready naming and the data signals are
not named by direction but type (read/write) [2].

 * Interface width: This was 'legacy', I extended the general
specification already to include 16, 32 and 64 bit interfaces. I added
a REG_WIDTH parameter and some note on smaller accesses. This is not
perfectly thought through so far and may need a further revision [3].

 * Timing specification of valid and ready: You made a good point the
formulation has some missing cases :) I am tending to say valid cannot
be de-asserted as this can lead to undefined behavior (control
initiated, ready delayed for action to have succeeded, but valid has
gone, what does this imply?). But I am open to other schemes. Thanks
for your offer to add a timing diagram, highly appreciated!

 * IRQ: Seems a good starting point for now. I assume you plan to put
the trap cause in IRQ_CAUSE register, right?

Best,
Stefan

[1]
https://github.com/opensocdebug/hardware/commit/9277dd4394edc73ed8c96e82
3ee005e10034dc13

[2]
https://github.com/opensocdebug/hardware/commit/dc205096f0cf238f0ac6fbce
c15503c16e8bc024

[3]
https://github.com/opensocdebug/hardware/commit/98c174274442cde526d1c698
2289db28fc0060fd
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