[Open SoC Debug] Overview document

Stefan Wallentowitz stefan at wallentowitz.de
Tue Feb 2 16:00:04 CET 2016

Hash: SHA1

On 01.02.2016 20:31, Tim Newsome wrote:
> Hi Stefan,

Hi Tim,

> This looks like a nice clean design overall.


> I have one big question: how do you deal with buffer on the host 
> interface module filling up? If it's talking over JTAG and eg. all
> cores hit a breakpoint at the same time, you might need to buffer
> one message from each core. (You actually mention this in the
> context of trace, but there you accept the message being dropped.)

There is a buffer in the Hardware Interface Module. If this one fills
up, it will backpressure to the interconnect and this will propagate
backpressure to the debug modules in worst case.

For the scenario you describe, that sufficiently handles it, because
the information is flowing out to the host as the buffer drains. While
the information cannot be send, the processor core is halted already
and the debug module can wait with generating the event in worst case.

For trace events it is slightly different, because a backpressure in
the debug subsystem cannot be propagated to the core interface (that
also the reason it only has enable, no ack). If it could, thats
intrusive to the execution what we don't want.

Thanks for pointing out, I will try to make it more clear later today
or tomorrow and run it back to you.

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