[Open SoC Debug] Software Trace Module specification

Stefan Wallentowitz stefan at wallentowitz.de
Sat Jan 23 09:01:30 CET 2016


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Hi all,

beside the run-control debug interface, we put the major focus on
trace debugging and I believe software tracing is an important feature.

I have roughly drafted the idea of the software trace module (stm) on
Github [1].

There has been a prototype implementation of this for the OpenRISC
core, which is available at [2].

The plan is to finalize the baseline spec [3] and have this as one of
the first modules in both lowRISC and the new OpTiMSoC debug system.

Looking forward to your input!

Best,
Stefan

[1]:
https://github.com/opensocdebug/hardware/blob/master/modules/stm/doc/specification.md

[2]:
https://github.com/optimsoc/sources/blob/master/src/rtl/debug_system/verilog/stm.v

[3]:
https://github.com/opensocdebug/documentation/blob/master/spec_base/specification.md
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