[Open SoC Debug] packet vs. memory interface

Stefan Wallentowitz stefan at wallentowitz.de
Thu Jan 28 11:40:49 CET 2016

Hash: SHA1

On 27.01.2016 20:42, Tim Newsome wrote:

> My thoughts here are that this is a lot of overhead if all you
> care about is accessing memory mapped registers. It seems more 
> straightforward to implement a protocol that doesn't require an
> extra layer of packet format on top of a memory bus. Am I
> overestimating the extra complexity here?
> Having said that, I understand why you arrived at this design. You 
> started with a bus for trace, and once you have that you may as
> well use it for debug as well.
> I'm coming at it from the other side, which is to specify a debug 
> interface with minimum extra features, so I used the system bus.
> If proper trace is to be added, it'll have to use a separate bus,
> but not everybody wants to spend the resources required for that.


I will go into the details in different e-mails as it has multiple
levels. Firstly, it is important, that we are talking about
run-control debugging, which is as you correctly said more like an
uncritical (low throughput) extra-feature.

In run-control debug there traditionally is a core debug interface.
RISC-V did not define one and Tim currently works on the spec [1]. I
have put my thoughts in the RISC-V debug group [2]

The current spec pretty much converges into the direction that it can
be straight-forward integrated either with the Open SoC Debug debug
ring, via a system bus (as Pulp is planning and you are partly) or a
JTAG adapter like Richard is doing. I am really happy to see this
going forward currently. I will put up an email summarizing the
current state of discussion as there are many threads (unfortunately
many private) flowing around this.


[1] https://goo.gl/Fsfjgu (does not work for me at the moment)
Version: GnuPG v2


More information about the OpenSoCDebug mailing list