[Open SoC Debug] Queries Regarding GSoC and Open SoC
anant16129 at iiitd.ac.in
Sun Feb 25 19:00:43 CET 2018
I have set up my environment and ready to go. I faced a little problem
because my system couldn't find or1k-elf-gcc, but I kind of fixed it. (I
don't think there's anything wrong with the python script). Also, went
through the examples of the Verilator. I am all set. What can I do next?
BTech - ECE,
On Thu, Feb 22, 2018 at 9:11 PM, Philipp Wagner <mail at philipp-wagner.com>
> [Forwarding this mail to the public OSD mailing list. Please reply there.]
> Hi Anant,
> both projects you chose require a bit more advanced understanding of
> Verilog and system-on-chip hardware design. I'm not sure if you'll be able
> to successfully complete these projects by reading your resume, but there
> is an easy way to figure it out yourself: trying!
> From the two projects you mentioned I'd recommend taking the run-control
> debug (GDB) one, since that should be easier to get started with.
> To see if you'll be able to make yourself at home at a larger code base,
> please try to setup OpTiMSoC (which contains Open SoC Debug) and work
> through the tutorials. You can find the instructions here:
> https://www.optimsoc.org/docs/master/user_guide/installation.html (Note
> that currently the dependency installation documentation seems to be not
> updated from the source, you can find the correct documents regarding this
> part here: https://github.com/optimsoc/optimsoc/blob/master/doc/user_gu
> For the OSD run-control GSoC task you don't need an FPGA board, all work
> can be done in simulation using Verilator. Hence it's sufficient to work
> through the Verilator examples in OpTiMSoC.
> So: give it a try and let me know if you face any problems along the way.
> On 02/20/2018 11:33 AM, Anant Sharma wrote:
>> I am sorry, that was my bad.
>> Anant Sharma,
>> BTech - ECE,
>> IIIT Delhi,
>> Ph: 9718827023
>> On Tue, Feb 20, 2018 at 2:30 AM, Philipp Wagner <mail at philipp-wagner.com
>> <mailto:mail at philipp-wagner.com>> wrote:
>> I think you forgot the attachment?
>> On 02/20/2018 10:08 AM, Anant Sharma wrote:
>> Hi Philipp,
>> I am Anant Sharma from IIIT Delhi pursuing my Bachelor's Degree
>> in Electronics and Communication Engineering. Its been 6 months
>> since I have started working on FPGA boards and have a basic to
>> intermediate understanding of Verilog. I have done some lab
>> projects on FPGAs which included projects which had
>> implementations of finite state machines and use of external
>> elements like PMOD Keypads and External 7 segment display.
>> I am interested in learning more and expanding my experience
>> with Embedded Systems and not just use my previous knowledge to
>> contribute something. I want to contribute to the community and
>> in turn learn something for myself. So from my last semester, I
>> have started developing interest in the field of Systems and
>> took up some classes about operating systems. Other than that, I
>> know how to code in the C language but haven't had good projects
>> where I used the language extensively.
>> I have achieved a lot of projects (check out my attached resume)
>> but the above were more relevant to the projects I am talking to
>> you about. I am very interested in the Open SoC debug: Run
>> Control Debugging and Trace logging to memory projects. All I
>> understand before any contact with anyone regarding the project
>> is the problem statement and the workflow that the project will
>> Honestly, I picked up one of the ideas from the list which I
>> thought were awesome if they are completed as I myself
>> understand the wide applications and scope. I am very interested
>> but I am not sure of exactly how would I proceed. It would be
>> great if you can guide me. It would be great if you could help
>> me get started.
>> Thank You,
>> Anant Sharma
>> Undergraduate Student
>> Electronics and Communication
>> IIIT Delhi
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