[Open SoC Debug] Queries Regarding GSoC and Open SoC

Anant Sharma anant16129 at iiitd.ac.in
Fri Mar 9 09:43:31 CET 2018


Hey, I was out of station and couldn't do a lot of work. Back on track now.
Was going
through some problems, can you please help me out?

On Mon, Feb 26, 2018 at 1:33 AM, Philipp Wagner <philipp.wagner at tum.de>
wrote:

> So back to the debug interface of the processor. To see that interface
> in action, you could try your first hardware modification.
>
> - Take the simplest example in OpTiMSoC, the compute_tile_dm with a
> single core running in Verilator. You have already built that design
> when working through the tutorial. However, now you need to re-build it
> frequently. To do so make use of fusesoc directly as it is documented
> here: https://www.optimsoc.org/docs/master/user_guide/develop.html
>
When I run the command fusesoc sim optimsoc:tile:compute_tile_dm
I get an error message saying "No tool was supplied to the command
line or found in 'optimsoc:tile:compute_tile_dm' core description"
I tried to work around it but wasn't able to. I think these problems are
arising due to my lack of understanding of the code base.

P.S. Already sourced optimsoc-environment.sh and setup-prebuilt.sh

By the time I will try to add the verilog code for the debug port.
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