[Open SoC Debug] Queries Regarding GSoC and Open SoC

Philipp Wagner philipp.wagner at tum.de
Fri Mar 9 11:19:29 CET 2018


On 03/09/2018 09:43 AM, Anant Sharma wrote:
> Hey, I was out of station and couldn't do a lot of work. Back on track 
> now. Was going
> through some problems, can you please help me out?
> 
> On Mon, Feb 26, 2018 at 1:33 AM, Philipp Wagner <philipp.wagner at tum.de 
> <mailto:philipp.wagner at tum.de>> wrote:
> 
>  > So back to the debug interface of the processor. To see that interface
>  > in action, you could try your first hardware modification.
>  >
>  > - Take the simplest example in OpTiMSoC, the compute_tile_dm with a
>  > single core running in Verilator. You have already built that design
>  > when working through the tutorial. However, now you need to re-build it
>  > frequently. To do so make use of fusesoc directly as it is documented
>  > here: https://www.optimsoc.org/docs/master/user_guide/develop.html 
> <https://www.optimsoc.org/docs/master/user_guide/develop.html>
>  >
> When I run the command fusesoc sim optimsoc:tile:compute_tile_dm
> I get an error message saying "No tool was supplied to the command
> line or found in 'optimsoc:tile:compute_tile_dm' core description"
> I tried to work around it but wasn't able to. I think these problems are
> arising due to my lack of understanding of the code base.

It's hard to see where exactly the problem is if I don't see the full 
command line and its outputs. However, in this case it's quite clear: 
you're trying to simulate an arbitrary module, not one of the examples.

Try

fusesoc --cores-root=/path/to/your/optimsoc/checkout/examples sim 
optimsoc:examples:compute_tile_sim

and you should get a running simulation of a single compute tile. (Equal 
to what is mentioned here: 
https://www.optimsoc.org/docs/master/user_guide/develop.html).

Philipp


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