[Open SoC Debug] Queries Regarding GSoC and Open SoC

Anant Sharma anant16129 at iiitd.ac.in
Fri Mar 9 11:36:13 CET 2018


On Fri, Mar 9, 2018 at 3:49 PM, Philipp Wagner <philipp.wagner at tum.de>
wrote:
>
> On 03/09/2018 09:43 AM, Anant Sharma wrote:
>>
>> Hey, I was out of station and couldn't do a lot of work. Back on track
now. Was going
>> through some problems, can you please help me out?
>>
>> On Mon, Feb 26, 2018 at 1:33 AM, Philipp Wagner <philipp.wagner at tum.de
<mailto:philipp.wagner at tum.de>> wrote:
>>
>>  > So back to the debug interface of the processor. To see that interface
>>  > in action, you could try your first hardware modification.
>>  >
>>  > - Take the simplest example in OpTiMSoC, the compute_tile_dm with a
>>  > single core running in Verilator. You have already built that design
>>  > when working through the tutorial. However, now you need to re-build
it
>>  > frequently. To do so make use of fusesoc directly as it is documented
>>  > here: https://www.optimsoc.org/docs/master/user_guide/develop.html <
https://www.optimsoc.org/docs/master/user_guide/develop.html>

So I got a little confused here, you mentioned compute_tile_dm here. I know
what you mean now. Thank You!
I ll get back to you when I m done with the next task!
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