[Open SoC Debug] GSoC project to improve soft-CPU debugging in LiteX + MiSoC

SHIVAM AGGARWAL shivam16195 at iiitd.ac.in
Mon Mar 19 16:09:26 CET 2018


*I am Shivam Aggarwal, currently pursuing my Bachelor’s in Electronics and
Communication Engineering from IIIT Delhi, India. I am quite passionate
about working with FPGAs and Verilog. I have worked with Basys 3 board,
Zynq board, Atlys board using Verilog and also underwent a course on
Embedded Systems. Apart from that, I am currently working on Dynamic
Partial Reconfiguration in Zynq board to implement Multi Standard Wireless
Transceiver. I have also worked with Python and have a very good experience
in Java as well. Currently, I am working with Timvideos.us and researching
about this issue #issue 39
<https://github.com/timvideos/getting-started/issues/39> to create a
generic debug system for soft CPU cores(or1k, lm32, risc-v) and a GDB
server as a part of GSOC project. I looked at some emails from the last
year's archives at OpenSOC. Tim introduced the project on the mailing list
and some constructive discussion was carried out. A rough outline of how
the project could be implemented was also discussed:
current progress:1. I have thoroughly read about JTAG, OpenOCD, adv_dbg_sys
implemented by opencores.2. I also read the documentation of OpenSOC and in
the process of setting up the development environment for the same.3.
Initially, I propose to tackle the project using the architecture
implementation of adv_dbg_sys but OpenSOC seems to be a better
alternative.I am quite interested in the project and would like to
implement the project as a part of this year's GSOC. I believe a lot of
things are already implemented as a part of OpenSOC project and can be used
in this project. It would be great if someone could provide a rough outline
of the project and guide me for the same.Looking forward to your valuable
suggestions for the project.ThanksShivam AggarwalPotential GSOC student *
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