[Open SoC Debug] GSoC Proposal | To improve soft-CPU debugging in LiteX + MiSoC

Philipp Wagner philipp.wagner at tum.de
Mon Mar 26 14:56:53 CEST 2018


Hi,

On 03/26/2018 02:46 PM, SHIVAM AGGARWAL wrote:
>         Now, you mentioned in the last mail, regarding osdacceess register
> 
>                                                     ^^^^^^^^^^^^^^^^^^^^^
>                                          There is no module with that name.
> 
> Sorry for the mistake. I actually meant osd_regaccess verilog 
> module.  Using osd_regaccess module, I can forward the register access 
> requests to the debug ports of the mor1kx core (the one with the du_* 
> signal names in the mor1kx implementation), right?
> 
> The only inputs to regaccess module are clk, rst, debug_in and 
> debug_out_ready. So, if debug_in = 1, the module is ready to accept 
> debug access request and if debug_out_ready = 1, then the request made 
> by the module is asserted.

Have a look at this code please: 
https://github.com/opensocdebug/osd-hw/blob/osd-next/modules/ctm/common/osd_ctm.sv#L70

If you look down to line 86 you can see how you can add reads to the 
registers 0x200 and 0x201.

These are 16 bit register reads, however. What we need for the interface 
with the mor1kx module are 32 bit registers. Hence you'll need to extend 
the osd_regaccess module to support registers with a different width 
than 16 bit.

Philipp


More information about the OpenSoCDebug mailing list