[Open SoC Debug] CDM-OR1K implementation

SHIVAM AGGARWAL shivam16195 at iiitd.ac.in
Sat May 19 16:20:24 CEST 2018


Hi,

Thanks for the guidance.
On Sat, 19 May 2018, 15:21 Stafford Horne, <shorne at gmail.com> wrote:

> Hi Philipp / Shivam,
>
> On Sat, May 19, 2018 at 12:42 AM, Philipp Wagner <philipp.wagner at tum.de>
> wrote:
> >
> > You didn't miss anything, and in fact the specification (as now
> published here http://opensocdebug.readthedocs.io/en/latest/02_
> spec/07_modules/cdm/dbgregisters.html) is pretty much all about
> forwarding registers (starting at 0x400).
>
> Thanks for the updated spec its coming together well.  I have some
> basic questions suggestions.  Please let me know what you think.
>
> *Register Access*
> How do we access the core's general purpose registers and (on
> openrisc) SPRs.    I just see mappings for the debug registers.  Is it
> in some other debug module? I thought it should be here.
>

As per my understanding, we will use CDM module to access only the debug
unit using signals defined in the System Interface. All the other registers
can be accessed through MAM (Memory Access Module).

*Stall Packet (CDM->debugger)*
> In the stall packet I see we encode the "reason", I don't think we
> need it. This would require that the CDM core know how to figure that
> out.  i.e. it would have to read the DRR to detect it was a trap, then
> it would need to check DMR2[WBS] to determine what caused the trap.
> I think the stall packet should specify "stall" only and core id if
> needed.   Note there are multiple things that might cause a stall
> (Timers, Debug Traps, Bus Error, Reset) we might want to capture all
> of those some day)
>

Yes. This part of specification is still pretty experimental.
I kept the description very minimal for this part for now. I believe for a
start, just a stall signal should be sufficient.

*Stall Packet (debugger->CDM) - missing?*
> I think we also need a packet to stall and restart the core.  I don't see
> this.
>

I think you are right. We need some means to allow debugger to stop the CPU
core. Subnet Control Module already provides this functionality.
https://opensocdebug.readthedocs.io/en/latest/02_spec/07_modules/scm/dbgregisters.html
For this part, we can have one more register in the control register map.
Setting this register high should be enough to stall and restart the core.

Please correct me if I am wrong.

>
> -Stafford
>
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