[Open SoC Debug] CDM-OR1K implementation

Stafford Horne shorne at gmail.com
Sat May 19 17:51:33 CEST 2018


On Sat, May 19, 2018 at 04:52:51PM +0200, Philipp Wagner wrote:
 
> >     *Stall Packet (debugger->CDM) - missing?*
> >     I think we also need a packet to stall and restart the core.  I
> >     don't see this.
> > 
> > 
> > I think you are right. We need some means to allow debugger to stop the
> > CPU core. Subnet Control Module already provides this functionality.
> > https://opensocdebug.readthedocs.io/en/latest/02_spec/07_modules/scm/dbgregisters.html
> > For this part, we can have one more register in the control register
> > map. Setting this register high should be enough to stall and restart
> > the core.
> 
> - I would expect a stall to be done using a OSD register write, not
> using an event packet. Event packets are there utilized for unsolicited
> events, i.e. things which cannot be anticipated by the host CPU when
> they happen.

I would agree, it just needs to be a register write.  It might be good, if
the procedure was async something like:

Stall
 1. REG write "stall request" bit in some register
 2. CDM sends "stall" event packet to notify the debugger of the stall complete

Resume
 1. REG write "start request" bit in some register
 2. ? What would be the best way to ensure th CPU resumed? Polling or another
    kind of Event packet?  I vote a "start ack" Event packet. (we could check
    how adv_dbg_if does it)

(This might be overkill)

That also brings up something else, we need a status register with a
running/stalled bit and maybe (start_pending/stall_pending).

In adb_dbg_if its a single bit per cpu

  Stall CPUn
  Set to '1' to suspend execution in the CPUn. Set to '0' to resume. Will be set
  to '1' automatically when a breakpoint indicator arrives from the CPU.




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