[Open SoC Debug] CDM-OR1K implementation

Stafford Horne shorne at gmail.com
Sat May 19 11:50:48 CEST 2018

Hi Philipp / Shivam,

On Sat, May 19, 2018 at 12:42 AM, Philipp Wagner <philipp.wagner at tum.de> wrote:
> You didn't miss anything, and in fact the specification (as now published here http://opensocdebug.readthedocs.io/en/latest/02_spec/07_modules/cdm/dbgregisters.html) is pretty much all about forwarding registers (starting at 0x400).

Thanks for the updated spec its coming together well.  I have some
basic questions suggestions.  Please let me know what you think.

*Register Access*
How do we access the core's general purpose registers and (on
openrisc) SPRs.    I just see mappings for the debug registers.  Is it
in some other debug module? I thought it should be here.

*Stall Packet (CDM->debugger)*
In the stall packet I see we encode the "reason", I don't think we
need it. This would require that the CDM core know how to figure that
out.  i.e. it would have to read the DRR to detect it was a trap, then
it would need to check DMR2[WBS] to determine what caused the trap.
I think the stall packet should specify "stall" only and core id if
needed.   Note there are multiple things that might cause a stall
(Timers, Debug Traps, Bus Error, Reset) we might want to capture all
of those some day)

*Stall Packet (debugger->CDM) - missing?*
I think we also need a packet to stall and restart the core.  I don't see this.


More information about the OpenSoCDebug mailing list