[Open SoC Debug] CDM-OR1K implementation

Philipp Wagner philipp.wagner at tum.de
Tue May 22 09:17:01 CEST 2018


Hi,

On 05/19/2018 05:51 PM, Stafford Horne wrote:
> On Sat, May 19, 2018 at 04:52:51PM +0200, Philipp Wagner wrote:
>   
>>>      *Stall Packet (debugger->CDM) - missing?*
>>>      I think we also need a packet to stall and restart the core.  I
>>>      don't see this.
>>>
>>>
>>> I think you are right. We need some means to allow debugger to stop the
>>> CPU core. Subnet Control Module already provides this functionality.
>>> https://opensocdebug.readthedocs.io/en/latest/02_spec/07_modules/scm/dbgregisters.html
>>> For this part, we can have one more register in the control register
>>> map. Setting this register high should be enough to stall and restart
>>> the core.
>>
>> - I would expect a stall to be done using a OSD register write, not
>> using an event packet. Event packets are there utilized for unsolicited
>> events, i.e. things which cannot be anticipated by the host CPU when
>> they happen.
> 
> I would agree, it just needs to be a register write.  It might be good, if
> the procedure was async something like:
> 
> Stall
>   1. REG write "stall request" bit in some register
>   2. CDM sends "stall" event packet to notify the debugger of the stall complete

That's certainly possible, even though (in my experience with the mor1kx 
implementation) unnecessary, as stalls are immediate.

> Resume
>   1. REG write "start request" bit in some register
>   2. ? What would be the best way to ensure th CPU resumed? Polling or another
>      kind of Event packet?  I vote a "start ack" Event packet. (we could check
>      how adv_dbg_if does it)
> 
> (This might be overkill)

Same comment as above essentially: the stall and resume are immediate in 
the mor1kx implementation.

Regardless of the mor1kx specifics, we have two options for giving 
feedback to the host on a stall or resume:

1. Send an acknowledgement event packet.

2. Or: simply delay the register write acknowledgement 
(https://opensocdebug.readthedocs.io/en/latest/02_spec/03_dataformats.html#register-write-request-type-sub-req-write-reg). 


Option 2 is essentially blocking the host side until the acknowledgement 
arrives, but given that it's (a) a very short time span, and (b) this 
behavior is actually what we're looking for, I'm voting for that option.

> That also brings up something else, we need a status register with a
> running/stalled bit and maybe (start_pending/stall_pending).
> 
> In adb_dbg_if its a single bit per cpu
> 
>    Stall CPUn
>    Set to '1' to suspend execution in the CPUn. Set to '0' to resume. Will be set
>    to '1' automatically when a breakpoint indicator arrives from the CPU.

Each CDM module is hooked up to a single CPU core, so no need for a 
multi-bit value. But the register write to to stall the CPU should also 
be readable, representing if the CPU is currently stalled.

Philipp



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