[Open SoC Debug] CDM-OR1K implementation

SHIVAM AGGARWAL shivam16195 at iiitd.ac.in
Fri May 25 09:04:40 CEST 2018


On Fri, May 25, 2018 at 12:28 PM, Philipp Wagner <philipp.wagner at tum.de>
wrote:

> On 05/24/2018 11:52 PM, Stafford Horne wrote:
>
>> Stafford and Shivam, is this matching your understanding as well? If there
>>> are significant differences in understanding maybe we should schedule a
>>> video call to get this sorted out quickly.
>>>
>>
>> Yes, this matches 100%.  I think this is basically what we need in the
>> spec.
>>
>
> Great, thanks for confirming Stafford! Shivam, the next step is now to put
> all this into an update of the spec. Now that we've essentially eliminated
> all or1k-specific parts it can also be renamed to CDM (removing the OR1K
> postfix).
>

Cool. Just a couple of queries.

1. The final mapping will be something like this:
https://docs.google.com/document/d/1qlmbhIvUt8XnSjvwAyiwyRDp6zeeJtN1Lz6WafBWn2o/edit?usp=sharing
, right?

2. Since, we are mapping each SPR into exactly one OSD register, we need to
change the width of the OSD register from 16 bits to 32 bits, right? or we
are going to store the MSB part of data in CORE_REG_UPPER for every
read/write transaction?

3. If point 2 is correct, then we need to map only first 10 groups in the
module. This implies that MSB for each group will always be 0. So, we can
even omit the CORE_REG_UPPER part.



> Philipp
>
>
Shivam
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